library IEEE;
use IEEE.std_logic_1164.all;

entity lab1 is 
   port( SW    :  IN    std_logic_vector( 9 downto 0 );
         HEX0  :  OUT   std_logic_vector( 6 downto 0 );
         HEX1  :  OUT   std_logic_vector( 6 downto 0 ) );
end entity;

architecture structural of lab1 is
   -- Define the signals
   -- Each code converter requires 7 signals coming out of it
   signal codeConv1  :  std_logic_vector( 6 downto 0 );
   signal codeConv2  :  std_logic_vector( 6 downto 0 );
   signal codeConv3  :  std_logic_vector( 6 downto 0 );
   signal codeConv4  :  std_logic_vector( 6 downto 0 );
   
   -- Define the components
   --------
   -- MUX2
   --------
   component MUX2
      port( sel   :  IN    std_logic;
            A, B  :  IN    std_logic;
            output:  OUT   std_logic );
   end component;
   
   -------------------
   -- Code Converters
   -------------------
   component codeConverter1
      port( SW    :     IN    std_logic_vector  (  1  downto   0  );
            hex   :     OUT   std_logic_vector  (  6  downto   0  ) );
   end component;
   
   component codeConverter2
      port( SW    :     IN    std_logic_vector  (  1  downto   0  );
            hex   :     OUT   std_logic_vector  (  6  downto   0  ) );
   end component;
   
   component codeConverter3
      port( SW    :     IN    std_logic_vector  (  1  downto   0  );
            hex   :     OUT   std_logic_vector  (  6  downto   0  ) );
   end component;
   
   component codeConverter4
      port( SW    :     IN    std_logic_vector  (  1  downto   0  );
            hex   :     OUT   std_logic_vector  (  6  downto   0  ) );
   end component;
   
begin
   -- Instantiate the code converters
   -- Code Converter 1
   cc1         :  codeConverter1
      port map(   SW     => SW( 2 downto 1 ),
                  hex    => codeConv1        );
   
   -- Code Converter 2
   cc2         :  codeConverter2
      port map(   SW     => SW( 4 downto 3 ),
                  hex    => codeConv2        );

   -- Code Converter 3
   cc3         :  codeConverter3
      port map(   SW     => SW( 7 downto 6 ),
                  hex    => codeConv3        );
   
   -- Code Converter 4
   cc4         :  codeConverter4
      port map(   SW     => SW( 9 downto 8 ),
                  hex    => codeConv4        );
   
   -- Instantiate the muxes, 14 are needed
   -- Instantiate the muxes for the code converters 1 and 2
   mux0_0      :  MUX2
      port map(   sel    => SW(0),
                  A      => codeConv1(0),
                  B      => codeConv2(0),
                  output => HEX0(0)          );
                  
   mux0_1      :  MUX2
      port map(   sel    => SW(0),
                  A      => codeConv1(1),
                  B      => codeConv2(1),
                  output => HEX0(1)          );
      
   mux0_2      :  MUX2
      port map(   sel    => SW(0),
                  A      => codeConv1(2),
                  B      => codeConv2(2),
                  output => HEX0(2)          );
                  
   mux0_3      :  MUX2
      port map(   sel    => SW(0),
                  A      => codeConv1(3),
                  B      => codeConv2(3),
                  output => HEX0(3)          );      

   mux0_4      :  MUX2
      port map(   sel    => SW(0),
                  A      => codeConv1(4),
                  B      => codeConv2(4),
                  output => HEX0(4)          );
                  
   mux0_5      :  MUX2
      port map(   sel    => SW(0),
                  A      => codeConv1(5),
                  B      => codeConv2(5),
                  output => HEX0(5)          );
                  
   mux0_6      :  MUX2
      port map(   sel    => SW(0),
                  A      => codeConv1(6),
                  B      => codeConv2(6),
                  output => HEX0(6)          );
   
   
   -- Instantiate the muxes for the code converters 3 and 4
   mux1_0      :  MUX2
      port map(   sel    => SW(5),
                  A      => codeConv3(0),
                  B      => codeConv4(0),
                  output => HEX1(0)          );
                  
   mux1_1      :  MUX2
      port map(   sel    => SW(5),
                  A      => codeConv3(1),
                  B      => codeConv4(1),
                  output => HEX1(1)          );
      
   mux1_2      :  MUX2
      port map(   sel    => SW(5),
                  A      => codeConv3(2),
                  B      => codeConv4(2),
                  output => HEX1(2)          );
                  
   mux1_3      :  MUX2
      port map(   sel    => SW(5),
                  A      => codeConv3(3),
                  B      => codeConv4(3),
                  output => HEX1(3)          );      

   mux1_4      :  MUX2
      port map(   sel    => SW(5),
                  A      => codeConv3(4),
                  B      => codeConv4(4),
                  output => HEX1(4)          );
                  
   mux1_5      :  MUX2
      port map(   sel    => SW(5),
                  A      => codeConv3(5),
                  B      => codeConv4(5),
                  output => HEX1(5)          );
                  
   mux1_6      :  MUX2
      port map(   sel    => SW(5),
                  A      => codeConv3(6),
                  B      => codeConv4(6),
                  output => HEX1(6)          );  
end structural;
      
      
      
